Getting Started: Quartus Prime & OpenOCD

Prerequisites

• Quartus Prime
• A SpiderSoM or MX10 with SpiderBase
• One of the following:
  • OpenOCD (Linux only)
  • USB Blaster and Quartus Programmer

Quartus Prime Project

1. Create a new Quartus Prime Project. Name the project Example, this will set our top level entity for later. Choose the correct FPGA, the remaining settings can be left default.
2. Go to Assignments -> Device -> Device and Pin Options -> Voltage and select 3.3-V LVCMOS as Default I/O Standard.
3. If you plan to use OpenOCD, you can enable automatically creating a .svf file. Under Device and Pin Options -> Programming Files select Serial Vector Format File (.svf).
4. Open the new file dialog and create a VHDL file.
5. Copy and paste the code below.
6. Save the VHDL file. This file contains our top level entity Example, which matches our project configuration.
7. Run Analysis & Elaboration (Processing -> Start -> ...), this will create nodes for pin assignment.
8. Open Pin Planner and edit the location for the existing signals:

   Node Name	SpiderSoM	MX 10
   button[1]	PIN_A5	PIN_T13
   button[0]	PIN_B7	PIN_T7
   led[1]	PIN_L2	PIN_T6
   led[0]	PIN_L1	PIN_T12
   clk25	PIN_H4	PIN_F9

   For a complete pin assignment table see here.

9. Run Compilation (Processing -> ...)
10. The subfolder output_files now contains an Example.sof file, an Example.pof file and if enabled the respective .svf files.
    .sof directly configures the FPGA. This configuration will be lost when the FPGA powers down.
    .pof writes to flash memory. When the FPGA powers up, it will load the configuration stored in the flash memory.
11. After programming the FPGA via OpenOCD or USB Blaster the yellow LED on the base should start blinking and the green LED lights up if exactly one user button is pressed.

VHDL Code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Example is
	port (
		clk25	: in	std_logic;
		button	: in	std_logic_vector(1 downto 0);
		led	: out	std_logic_vector(1 downto 0)
	);
end entity Example;



architecture archExample of Example is

	signal counter : integer range 1 to 12500000 := 1;
	signal led_yellow : std_logic := '0';

begin

	process (clk25)
	begin
		if (clk25 = '1' and clk25'EVENT) then
			if (counter < 12500000) then
				counter <= counter + 1;
			else
				led_yellow <= not led_yellow;
				counter <= 1;
			end if;
		end if;				
	end process;
	
	led(1) <= led_yellow;
	led(0) <= button(0) xor button(1); 

end architecture archExample;

Programming via OpenOCD

1. Configuring OpenOCD
   1. Create aries-pic.cfg and altera-10m08s.cfg and insert content below.
   2. If you use a different FPGA than 10M08S, you may want to create an other file with updated idcode instead. (see below)
2. Convert the project files to a .svf File
   1. Automatically
      1. Before running Compilation go to Assignments -> Device -> Device and Pin Options -> Programming Files and select Serial Vector Format File (.svf).
      2. The .sof file will be located under /output_files/Example.svf and the .pof file under /output_files/Example_pof.svf.
   2. Manually
      1. In Quartus Prime, open the Programmer (Tools -> Programmer).
      2. Choose whether you want to use the .sof or the .pof file.
      3. Open File menu and select Create JAM, JBC, SVF or ISC File...
      4. Choose file format Serial Vector Format (.svf). Select filename or leave it as default.
3. Run OpenOCD
   1. Open a terminal window and type:

      $ openocd -f </pathto/aries-pic.cfg> -f </pathto/altera-10m08s.cfg>

   2. A new tap should now be created with the correct idcode.
4. Connect to OpenOCD via telnet
   1. Open another terminal window and type:

      $ telnet localhost 4444

   2. You should now be connected to your OpenOCD server.
   3. To run the .svf file type:

      svf /<path_to>/Example.svf

On a 10m02s the .sof file takes about 30 seconds and the .pof file about 3 minutes to program.

aries-pic.cfg

interface usb_blaster
usb_blaster_lowlevel_driver ftdi
usb_blaster_vid_pid 0x04d8 0xefd0

altera-10m08s.cfg

jtag newtap 10m08s tap -expected-id 0x31820dd -irlen 10

If you use a different MAX10 FPGA than the one above, replace name 10m08s and idcode 0x31820dd with values provided below.

Name	ID Code		Name	ID Code
10m02s	0x31810dd		10m02d	0x31010dd
10m04s	0x318a0dd		10m04d	0x310a0dd
10m08s	0x31820dd		10m08d	0x31020dd
10m16s	0x31830dd		10m16d	0x31030dd
10m25s	0x31840dd		10m25d	0x31040dd
10m40s	0x318d0dd		10m40d	0x310d0dd
10m50s	0x31850dd		10m50d	0x31050dd

Programming via USB Blaster

1. Connect the USB Blaster to the JTAG Header on the SpiderBase.
2. In Quartus Prime, open the Programmer (Tools -> Programmer).
3. Choose whether you want to use the .sof or the .pof file.
4. Click Hardware Setup... and select your USB Blaster, if there is none available you may need to start the jtag service.
5. Press Start