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− | == Prerequisites ==
| + | '''Under construction.''' |
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− | * Linux Operating System (this guide uses Ubuntu 16.04)
| + | For now follow the guide from the [https://github.com/ARIES-Embedded/riscv-on-max10/blob/master/GettingStarted.md repository]. |
− | * Utility Software (git, make, python)
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− | * [http://fpgasoftware.intel.com/?edition=lite Quartus Prime]
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− | * A [[Spiderboard_SoM|SpiderSoM]] or MX10<sup>[[Installing OpenOCD#MX10 Hardware Issue|[note]]]</sup> with atleast 8K LE, [[Spiderboard_Baseboard|SpiderBase]], optionally [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 LED Pmod]
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− | * One of the following:
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− | ** [[Installing OpenOCD|OpenOCD]]
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− | ** USB Blaster and Quartus Programmer
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− | == Installing VectorBlox ORCA Core and RISC-V Tools ==
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− | * Download the source from [https://github.com/VectorBlox/orca https://github.com/VectorBlox/orca] using git.
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− | *: This guide uses the install locations ''/opt/orca/'' and ''/opt/riscv/'', you can substitute them if you wish.
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− | * Open a terminal window and run:
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− | *: '''$''' <nowiki> git clone https://github.com/VectorBlox/orca.git /opt/orca </nowiki>
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− | *: '''$''' cd /opt/orca/tools/riscv-toolchain/
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− | *: '''$''' export RISCV_INSTALL="/opt/riscv"
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− | *: '''$''' ./build-toolchain.sh
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− | *:: Info: This may take a while.
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− | * Finally, add the RISC-V tools to your path. Open ''.profile'' in your home directory with a text exitor and add the line:
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− | *: PATH="/opt/riscv/bin:$PATH"
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− | * After updating the path variable you may need to logout and login again or run the following command in the terminal:
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− | *: '''$''' source ~/.profile
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− | == Compiling Firmware ==
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− | * Download the [https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
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− | * Then choose either RISC-V or RISC-V & FreeRTOS and run make.
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− | * Open a terminal window and run the commands:
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− | *: '''$''' wget <nowiki>https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip</nowiki>
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− | *: '''$''' unzip 20190604_mx10_spider_riscv_freertos.zip
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− | ** For the RISC-V standalone demo:
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− | **: '''$''' cd mx10_spider_riscv_freertos/riscv
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− | ** Or for RISC-V with FreeRTOS:
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− | **: '''$''' cd mx10_spider_riscv_freertos/riscv_freertos
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− | *: '''$''' make
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− | * This will create the ''bootrom.mif'' (Memory Initialization File) in the subfolder ''out''.
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− | * Copy the ''bootrom.mif'' to ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider'', depending on which module you use.
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− | *: '''$''' cp out/bootrom.mif ../quartus_spider
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− | [[File:terminal_make_riscv.png|1200px|Terminal after calling make.]]
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− | == Quartus Prime Project ==
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− | * Open Quartus Prime and load the project under ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider''
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− | * Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGA the MX10 project is the 10M08DAF256C8G FPGA and for the SpiderSoM project the 10M08SAU169C8G FPGA.
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− | * Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
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− | *: If ORCA was installed under ''/opt/orca/'' then type in as search path ''/opt/orca/**/*'' and click on the ''Add'' button.
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− | [[File:quartus_setting_iploc.png|700px|Type in the search path and then click on ''Add''.]]
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− | * (Optional) Launch Qsys Platform Designer and open ''qsys.qsys''
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− | ** (Optional) Under System Contents, double-click ''onchip_memory2_0'' and under memory initialization provide your bootrom.mif file. Per default the bootrom.mif in the quartus folder will be used.
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− | ** (Optional) Save and Generate the Qsys system.
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− | [[File:qsys-ram-init.png|900px|Setting the memory initialization in Qsys Platform Designer]]
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− | * Compile the project and program it onto the FPGA using either [[Getting Started: Quartus Prime & OpenOCD#Programming via OpenOCD | OpenOCD]] or [[Getting Started: Quartus Prime & OpenOCD#Programming via USB Blaster| USB-Blaster]].
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− | After programming:
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− | * If the red or orange LED on the module starts blinking once per second, the FPGA was programmed successfully.
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− | * If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
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− | * PMod J2 will output a binary counter.
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− | * You can use the UART of the FPGA by using standard tools such as picocom:
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− | *: '''$''' sudo picocom -b 115200 /dev/ttyACM0
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− | ** Every character written is looped back and should be displayed on the terminal.
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− | <div><ul>
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− | <li style="display: inline-block;"> [[File:spider-running-riscv-leds.png|x330px|thumb|Spider with LED PMod connected on J2 showing the binary counter. The LED PMod can be acquired in the [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 shop]]] </li>
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− | <li style="display: inline-block;"> [[File:terminal_picocom.png|x330px|thumb|Characters written are looped back and displayed.]] </li>
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− | </ul></div>
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− | == Downloads ==
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− | * [https://github.com/VectorBlox/orca VectorBlox ORCA]
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− | * [https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example]
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