Difference between revisions of "RISC-V & FreeRTOS"

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== Installing VectorBlox ORCA Core and RISC-V Tools ==
+
== Prerequisites ==
  
−
* Download the source from [https://github.com/VectorBlox/orca https://github.com/VectorBlox/orca] using git.
+
* Linux Operating System (this guide uses Ubuntu 20.04)
−
*: In this guide the install locations ''/opt/orca/'' and ''/opt/riscv/'' were chosen.
+
* Developer Tools (git, make, gcc, python (3))
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* Open a terminal window and run:
+
* [http://fpgasoftware.intel.com/?edition=lite Quartus Prime] (this guide uses version 20.1 Lite)
−
*: '''$''' <nowiki> git clone https://github.com/VectorBlox/orca.git /opt/orca </nowiki>
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* USB Blaster or [[Installing OpenOCD|OpenOCD]]
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*: '''$''' cd /opt/orca/tools/riscv-toolchain/
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* SpiderSoM-S, MX10-S8 or MX10-U
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*: '''$''' export RISCV_INSTALL="/opt/riscv"
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* optionally [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 LED Pmod]
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*: '''$''' ./build-toolchain.sh
 
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*:: Info: This may take a while.
 
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* Finally add the RISC-V tools to your path:
 
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*: '''$''' nano ~/.profile
 
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::: export PATH=/opt/riscv/bin:$PATH
 
  
−
== Compiling Firmware ==
+
'''Note:'''<br>
 +
Instructions starting with '''$''' are commands to be executed in the terminal.<br>
 +
The working directory is to be taken from context.
  
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* Download the [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
+
== RISC-V Cores ==
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* Open a terminal window, change directory to either ''riscv_freertos_example/riscv'' or ''riscv_freertos_example/riscv_freertos'' and run:
 
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*: '''$''' make
 
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* The folder ''out'' now contains the ''bootrom.mif'' (Memory Initalization File).
 
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* Copy the ''bootrom.mif'' to ''riscv_freertos_example/quartus''
 
  
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== Quartus Prime Project ==
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Three open source RISC-V cores have been made available for the Intel Platform Designer (Qsys).
  
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* Open Quartus Prime and load the project under ''riscv_freertos_example/quartus''.
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* [https://github.com/olofk/serv SERV]
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*: INFO: This Quartus project is specific to the SpiderSoM - for the MX10 the pin assignment has to be changed.
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* [https://github.com/cliffordwolf/picorv32 PicoRV32]
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* Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
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* [https://github.com/SpinalHDL/VexRiscv VexRiscv]
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*: If ORCA was installed under ''/opt/orca/'' then use as search path: ''/opt/orca/**/*''
 
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* (Optional) Open the Platform Designer with the Qsys file
 
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** (Optional) Under System Contents, double-click ''onchip_memory2_0'' and under memory initialization provide your bootrom.mif file. (The default is to use the bootrom.mif in the quartus folder)
 
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** (Optional) Save and Generate the Qsys system.
 
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* Compile the project and program it onto the FPGA using either [[Getting Started: Quartus Prime & OpenOCD#Programming via OpenOCD | OpenOCD]] or [[Getting Started: Quartus Prime & OpenOCD#Programming via USB Blaster| USB-Blaster]].
 
  
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After programming:
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To install the cores for Intel Platform Designer, first download the source from the [https://github.com/ARIES-Embedded/riscv-on-max10 GitHub repository].
 +
:'''$''' <nowiki> git clone https://github.com/ARIES-Embedded/riscv-on-max10.git </nowiki>
 +
Then copy the cores to a location such as '''/opt/riscv-cores'''
 +
:'''$''' cp --parents riscv-on-max10/RiscvCores /opt/riscv-cores
 +
Start Intel Quartus Prime and add the cores to the global library:
 +
: Open the menu '''Assignments''' -> '''Settings'''
 +
: Under '''IP Settings''' -> '''IP Catalog Search Locations''' add the path
 +
: '''/opt/riscv-cores/**/*''' to the global IP search directories
 +
Now the cores are available as IP under the group ''RISC-V''.
  
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* If the red LED on the module starts blinking once per second, the FPGA was programmed successfully.
+
== Programming The Demo ==
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* If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
 
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* PMod J2 will output a binary counter.
 
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* You can use the UART of the FPGA by using standard tools such as picocom:
 
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*: '''$''' sudo picocom -b 115200 /dev/ttyACM0
 
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** Every character written is looped back and should be displayed on the terminal.
 
  
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== Downloads ==
+
=== Compiling Firmware ===
  
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* [https://github.com/VectorBlox/orca VectorBlox ORCA]
+
A precompiled memory initialization file (.mif) is available in the '''Prebuild/''' folder, that can be used to skip this section.
−
* [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example]
+
 
 +
==== Installing The GNU GCC Toolchain ====
 +
 
 +
The complete guide for installing the toolchain can be found in the [https://github.com/riscv-collab/riscv-gnu-toolchain RISC-V GNU Toolchain repository].
 +
 
 +
Download and install the prerequisites:
 +
: '''$''' sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
 +
Clone the repository:
 +
: '''$''' git clone https://github.com/riscv-collab/riscv-gnu-toolchain
 +
Configure build with multilib support for RV32 architectures:
 +
: '''$''' cd riscv-gnu-toolchain
 +
: '''$''' ./configure --prefix=/opt/riscv --with-multilib-generator="rv32i-ilp32--;rv32im-ilp32-rv32ima-;rv32imc-ilp32-rv32imac-;rv32imafc-ilp32f--"
 +
Finally start the build, note that this can take some time!
 +
: '''$''' sudo make
 +
Add the build tools to the path variable by opening '''~/.bashrc''' or equivalent and add the line:
 +
: export PATH="$PATH:/opt/riscv/bin"
 +
Reload the terminal:
 +
: '''$''' source ~/.bashrc
 +
Now the build tools are available via:
 +
: '''riscv64-unknown-elf-(*)
 +
 
 +
==== Compiling The RISC-V Firmware ====
 +
 
 +
Open a terminal in the '''RiscvSimple/''' or '''RiscvFreertos/''' folder of one of the sample projects and run the command:
 +
:'''$''' make
 +
If successful the output files are generated in the subfolder '''out/'''.<br>
 +
Copy the '''bootrom.mif''' to the respective Quartus Project folder.
 +
:'''$''' cp out/bootrom.mif ..
 +
 
 +
=== Quartus Prime Project ===
 +
 
 +
==== Precompiled Files ====
 +
 
 +
Precompiled programming files are available for the modules, they can be used to skip the next section and start with [[#Programming the FPGA|programming the FPGA]].
 +
 
 +
==== Compiling The Quartus Project ====
 +
 
 +
Start Quartus Prime and open the project corresponding to your module.<br>
 +
Click on '''Start Compilation'''
 +
If successful, the programming files are generated in the folder '''output_files'''
 +
 
 +
==== Programming the FPGA ====
 +
 
 +
The FPGA stores its configuration in the internal SRAM.
 +
The configuration is lost when the device is powered down.
 +
At bootup the FPGA loads the configuration image from the internal FLASH to the SRAM.
 +
The '''.sof''' file will only write to the SRAM, usually used for testing and debugging,
 +
whereas the '''.pof''' file writes to the FLASH and reboots the FPGA. This image will then be loaded whenever the FPGA is powered on. The '''.pof''' file is usually used for deploying.
 +
 
 +
===== Programming Via USB-Blaster =====
 +
 
 +
Start Quartus Prime and open the Programmer.
 +
If no programming file is specified, click '''Add File''' and navigate to the '''Prebuild/''' or '''output_files''' folder and select the appropriate file for the module.
 +
Then under '''Hardware Setup...''' select the USB-Blaster.
 +
Finally press Start.
 +
 
 +
===== Programming Via OpenOCD =====
 +
If not done already install and configure [[Installing OpenOCD|OpenOCD]].
 +
Then open a terminal and use the command with the '''.svf''' file:
 +
: '''$''' mx10spider_prog ''<path/to/file.svf>''
 +
Example: To program the SpiderSoM with the prebuild "'''.sof'''" file.
 +
: '''$''' mx10spider_prog Prebuild/Spider_S.svf

Latest revision as of 17:19, 9 November 2021

Prerequisites

  • Linux Operating System (this guide uses Ubuntu 20.04)
  • Developer Tools (git, make, gcc, python (3))
  • Quartus Prime (this guide uses version 20.1 Lite)
  • USB Blaster or OpenOCD
  • SpiderSoM-S, MX10-S8 or MX10-U
  • optionally LED Pmod

Note:
Instructions starting with $ are commands to be executed in the terminal.
The working directory is to be taken from context.

RISC-V Cores

Three open source RISC-V cores have been made available for the Intel Platform Designer (Qsys).

To install the cores for Intel Platform Designer, first download the source from the GitHub repository.

$ git clone https://github.com/ARIES-Embedded/riscv-on-max10.git

Then copy the cores to a location such as /opt/riscv-cores

$ cp --parents riscv-on-max10/RiscvCores /opt/riscv-cores

Start Intel Quartus Prime and add the cores to the global library:

Open the menu Assignments -> Settings
Under IP Settings -> IP Catalog Search Locations add the path
/opt/riscv-cores/**/* to the global IP search directories

Now the cores are available as IP under the group RISC-V.

Programming The Demo

Compiling Firmware

A precompiled memory initialization file (.mif) is available in the Prebuild/ folder, that can be used to skip this section.

Installing The GNU GCC Toolchain

The complete guide for installing the toolchain can be found in the RISC-V GNU Toolchain repository.

Download and install the prerequisites:

$ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev

Clone the repository:

$ git clone https://github.com/riscv-collab/riscv-gnu-toolchain

Configure build with multilib support for RV32 architectures:

$ cd riscv-gnu-toolchain
$ ./configure --prefix=/opt/riscv --with-multilib-generator="rv32i-ilp32--;rv32im-ilp32-rv32ima-;rv32imc-ilp32-rv32imac-;rv32imafc-ilp32f--"

Finally start the build, note that this can take some time!

$ sudo make

Add the build tools to the path variable by opening ~/.bashrc or equivalent and add the line:

export PATH="$PATH:/opt/riscv/bin"

Reload the terminal:

$ source ~/.bashrc

Now the build tools are available via:

riscv64-unknown-elf-(*)

Compiling The RISC-V Firmware

Open a terminal in the RiscvSimple/ or RiscvFreertos/ folder of one of the sample projects and run the command:

$ make

If successful the output files are generated in the subfolder out/.
Copy the bootrom.mif to the respective Quartus Project folder.

$ cp out/bootrom.mif ..

Quartus Prime Project

Precompiled Files

Precompiled programming files are available for the modules, they can be used to skip the next section and start with programming the FPGA.

Compiling The Quartus Project

Start Quartus Prime and open the project corresponding to your module.
Click on Start Compilation If successful, the programming files are generated in the folder output_files

Programming the FPGA

The FPGA stores its configuration in the internal SRAM. The configuration is lost when the device is powered down. At bootup the FPGA loads the configuration image from the internal FLASH to the SRAM. The .sof file will only write to the SRAM, usually used for testing and debugging, whereas the .pof file writes to the FLASH and reboots the FPGA. This image will then be loaded whenever the FPGA is powered on. The .pof file is usually used for deploying.

Programming Via USB-Blaster

Start Quartus Prime and open the Programmer. If no programming file is specified, click Add File and navigate to the Prebuild/ or output_files folder and select the appropriate file for the module. Then under Hardware Setup... select the USB-Blaster. Finally press Start.

Programming Via OpenOCD

If not done already install and configure OpenOCD. Then open a terminal and use the command with the .svf file:

$ mx10spider_prog <path/to/file.svf>

Example: To program the SpiderSoM with the prebuild ".sof" file.

$ mx10spider_prog Prebuild/Spider_S.svf
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